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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using <t>ADS</t> <t>(Keysight</t> Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.
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Simulation process of an IDC on a glass substrate in air using ADS (Keysight Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.

Journal: Scientific Reports

Article Title: Inter-digital capacitors with aerosol-deposited high-K dielectric layer for highest capacitance value in capacitive super-sensing applications

doi: 10.1038/s41598-018-37416-7

Figure Lengend Snippet: Simulation process of an IDC on a glass substrate in air using ADS (Keysight Technologies). (a ) 3D view of the designed patterns, ( b ) layer arrangement for the bare chip, ( c ) the design with BaTiO3 films on top of the IDC, ( d ) thermal treatment of the chips.

Article Snippet: In our study, three IDCs with different finger widths and equal gaps were designed and simulated using the Advanced Design System (ADS) (2016.01, Keysight©).

Techniques: